1. Field of the Invention
The present invention generally relates to chemical mechanical planarization of oxides and more particularly to an improved method and structure that reduces or eliminates scratching of the oxides.
2. Description of the Related Art
During chemical mechanical planarization (CMP), the oxide that is used for device isolation in semiconductor processing is often scratched. Scratches in the oxide lead to reduction in wafer final test yields as these scratches can fill with conductive materials in downstream processes resulting in shorting of circuits. For example, in the silicon on insulator (SOI) process, after the initial oxide CMP, a second poly CMP process is needed for a substrate contact. The use of CMP twice in the isolation sector in SOI results in an unacceptable polish scratch defect density.
Current solutions focus on minimizing the number of scratches by improving slurries or pads used for CMP processes. These current solutions reduce, but do not eliminate scratches. In addition, as across wafer uniformity becomes increasingly important, the ‘harder’ pads used to improve uniformity increase scratch defect density. The current solutions also do not address minimizing the impact of a scratch once it is on the wafer.